Conventional computer systems include a processor (not shown) coupled to a variety of memory devices, including read-only memories (“ROMs”) which traditionally store instructions for the processor, and a system memory to which the processor may write data and from which the processor may read data. The processor may also communicate with an external cache memory, which is generally a static random access memory (“SRAM”). The processor also communicates with input devices, output devices, and data storage devices.
Processors generally operate at a relatively high speed. Processors such as the Pentium® and Pentium II® microprocessors are currently available that operate at clock speeds of at least 400 MHz. However, the remaining components of existing computer systems, with the exception of SRAM cache memory, are not capable of operating at the speed of the processor. For this reason, the system memory devices, as well as the input devices, output devices, and data storage devices, are not coupled directly to the processor bus. Instead, the system memory devices are generally coupled to the processor bus through a memory controller, bus bridge or similar device, and the input devices, output devices, and data storage devices are coupled to the processor bus through a bus bridge. The memory controller allows the system memory devices to operate at a clock frequency that is substantially lower than the clock frequency of the processor. Similarly, the bus bridge allows the input devices, output devices, and data storage devices to operate at a frequency that is substantially lower than the clock frequency of the processor. Currently, for example, a processor having a 300 MHz clock frequency may be mounted on a mother board having a 66 MHz clock frequency for controlling the system memory devices and other components.
Access to system memory is a frequent operation for the processor. The time required for the processor, operating, for example, at 300 MHz, to read data from or write data to a system memory device operating at, for example, 66 MHz, greatly slows the rate at which the processor is able to accomplish its operations. Thus, much effort has been devoted to increasing the operating speed of system memory devices.
System memory devices are generally dynamic random access memories (“DRAMs”). Initially, DRAMs were asynchronous and thus did not operate at even the clock speed of the motherboard. In fact, access to asynchronous DRAMs often required that wait states be generated to halt the processor until the DRAM had completed a memory transfer. However, the operating speed of asynchronous DRAMs was successfully increased through such innovations as burst and page mode DRAMs, which did not require that an address be provided to the DRAM for each memory access. More recently, synchronous dynamic random access memories (“SDRAMs”) have been developed to allow the pipelined transfer of data at the clock speed of the motherboard. However, even SDRAMs are typically incapable of operating at the clock speed of currently available processors. Thus, SDRAMs cannot be connected directly to the processor bus, but instead must interface with the processor bus through a memory controller, bus bridge, or similar device. The disparity between the operating speed of the processor and the operating speed of SDRAMs continues to limit the speed at which processors may complete operations requiring access to system memory.
A solution to this operating speed disparity has been proposed in the form of a packetized memory device known as a SLDRAM memory device. In the SLDRAM architecture, the system memory may be coupled to the processor, either directly through the processor bus or through a memory controller. Rather than requiring that separate address and control signals be provided to the system memory, SLDRAM memory devices receive command packets that include both control and address information. The SLDRAM memory device then outputs or receives data on a data bus that may be coupled directly to the data bus portion of the processor bus. A master clock signal transmitted to each memory device is used to synchronize data transfer between the processor and memory device and also serves as a basis from which to generate internal clock signals coordinating internal memory operations.
One of the factors limiting the access speed of SLDRAM memory devices is the speed at which the command buffer of each device can store and process the command packets. The processing speed of the command buffer is dependent on the control of the relative timing between transmission of the command packets from the processor and an internal clock signal ICLK of the memory device used to trigger a latch in the command buffer to capture the command signals. Both the command signals and the ICLK signal are delayed relative to receipt of the command packet on a command bus and a command clock signal CMDCLK. Furthermore, the amount of the delay is highly variable, and it is difficult to control. If the delay of the internal clock signal ICLK cannot be precisely controlled, it may cause the latch in the command buffer to latch invalid command signals. Thus, the speed at which command packets can be applied to the memory device is limited by the delays in the memory device. Similar problems exist for other control signals in the memory device that control the operation of the memory device during each clock cycle, such as latching of data in the memory device and in a memory controller.
Consequently, the operation of a SLDRAM memory architecture necessitates the generation of a sequence of clock signals having predetermined phases relative to a master clock signal. Phase-locked and delay locked loops have been employed to ensure the precise phase relationship between clock signals. In such a closed loop, there is typically a phase detector receiving two clock signals, and a voltage controlled delay circuit through which one clock signal passes. The voltage controlled delay circuit receives control signals from the phase detector that are used adjust the variable delay value in order to establish a predetermined phase relationship between the two clock signals. For example, where the desired phase relationship between two clock signals is zero degrees, the phase detector will detect any phase difference between the two clock signals and generate a control signal that is transmitted to the voltage controlled delay circuit. The delay circuit will adjust the delay value according to the control signal until the clock signal passing through the voltage controlled delay circuit is synchronized with the other clock signal. The clock control circuitry in an SLDRAM is described in greater detail in U.S. patent application Ser. Nos. 08/879,847, 08/890,055, 08/933,324, 08/994,461, 09/146,716, and 09/150,079, which are incorporated herein by reference.
A single phase detector connected to a CMOS inverter has been used as a means of providing a control signal to the above-described voltage controlled delay circuits. As shown in FIG. 1, clock signals CLK1 and CLK2 are applied to two pulse generating circuits 11, 12, each of which includes a NAND gate 16 receiving a respective clock signal directly and through three series connected inverters 18, 20, 22. The output of each pulse generating circuit 11, 12 set and reset a flip-flop 26 formed by cross-coupled NAND gates 28, 30. A single output of the flip-flop 26 is connected to the gates of an inverter 36 formed by a PMOS transistor 38 and an NMOS transistor 40. A current source 44 supplies current to the source of the PMOS transistor 38, and a current sink 46 draws current from the source of the NMOS transistor 40. When the output from the flip-flop 26 is low, the PMOS transistor 38 is turned ON and the NMOS transistor 40 is turned OFF. In this condition, a conductive path is created for the current source 44 to couple current to a capacitor 48. A control signal VOUT is generated by the capacitor 48. When the current source 44 is applying current to the capacitor 48, the voltage of the control signal VOUT increases linearly. In the alternative case where the output from the flip-flop 26 is high, the PMOS transistor 38 is switched OFF and the NMOS transistor 40 is switched ON. The current sink 46 is then coupled to the capacitor 48 to draw current from the capacitor 48. The voltage of the control signal VOUT then decreases linearly. As a result, the control signal VOUT has a sawtooth waveform component.
The problem with using a single phase detector connected to an inverter 36, as shown in FIG. 1, is that even after the voltage controlled delay circuit has been adjusted so the clock signals have the predetermined phase relationship, the circuit will nevertheless continue to generate a sawtooth ripple voltage at its output. The sawtooth waveform component of the control signal VOUT is transmitted to the voltage controlled delay circuit (not shown in FIG. 1), which is forced to constantly adjust the delay value, and consequently, the phase relationship between the two clock signals CLK1 and CLK2. The closed loop system will oscillate around a center-point and continue to “hunt” for the optimum control voltage value.
The result is a “phase jitter” imparted to clock signals used to latch command and data signals. Although the phase jitter introduced by the sawtooth ripple voltage may be acceptable in some applications, in high speed memory applications where the clock frequencies are high and the need to control the phase relationship between clock signals is critical, the clocks signals may fail to correctly latch command and data signals.
To accommodate the problems associated with the sawtooth ripple, the memory system designer may relax the timing requirements of the memory system by slowing down the clock frequencies and reducing the operating speed of the memory device. However, this approach defeats the primary purpose of developing high speed memory systems. Therefore, there is a need for a phase detector that generates a control signal that does not vary when the input clock signals have been adjusted to a predetermined phase relationship.